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# Makefile for testing python-uvm

# Usage:
# To execute tests in given file using given verilog source, you can do:
# >$ make MODULE=py_mod_name VLOG=hdl/my_vlog.v SIM_ARGS='-aaa +bbb'
#

include ../../MakefileCommon.mk
PYTHONPATH := $(WPWD)/../../../integrated:$(PYTHONPATH)

ifeq ($(TOPLEVEL_LANG),verilog)
    ifeq ($(IMG),BLK)
        VERILOG_SOURCES := $(WPWD)/blk_dut.sv
    else
        VERILOG_SOURCES := $(WPWD)/sys_dut.sv
    endif
else ifeq ($(TOPLEVEL_LANG),vhdl)
    ifeq ($(IMG),BLK)
        VHDL_SOURCES += $(WPWD)/blk_dut.vhd
    else
        VHDL_SOURCES += $(WPWD)/blk_dut.vhd
        VHDL_SOURCES += $(WPWD)/sys_dut.vhd
    endif
else
    $(error "A valid value (verilog) was not provided for TOPLEVEL_LANG=$(TOPLEVEL_LANG)")
endif


ifneq ($(VLOG),)
	VERILOG_SOURCES := $(VLOG)
endif

#PLUSARGS=+UVM_TESTNAME=ubus_example_base_test +UVM_CONFIG_DB_TRACE=1 +UVM_VERBOSITY=UVM_HIGH
#PLUSARGS=+UVM_TESTNAME=test_2m_4s +UVM_CONFIG_DB_TRACE=1 +UVM_VERBOSITY=UVM_HIGH
#PLUSARGS=+UVM_CONFIG_DB_TRACE=1 +UVM_VERBOSITY=UVM_HIGH
#ifneq ($(UVM_TEST),)
#    PLUSARGS += +UVM_TESTNAME=$(UVM_TEST)
#endif

ifneq ($(SIMARGS),)
    PLUSARGS += $(SIMARGS)
endif

ifeq ($(IMG),BLK)
    TOPLEVEL := blk_dut
    MODULE   ?= blk_run
else
    TOPLEVEL := sys_dut
    MODULE   ?= sys_run
endif

ifeq ($(SIM),$(filter $(SIM),ius xcelium))
    COMPILE_ARGS=-gpg "BASE_ADDR => 'h100" -v93
else
    ifeq ($(SIM), icarus)
        COMPILE_ARGS="-PBASE_ADDR='h100"
    endif
endif

include $(shell cocotb-config --makefiles)/Makefile.sim
